Position: Design Engineer
Location: IRVINE, CA
Duration: 7-18 months
USC or GCs are highly encouraged to apply
Required skills:
ANALYSIS; ASIC; ASIC DESIGN; Debug; RTL;
TESTING; UNIX; V
Solid knowledge of ASIC design flows and methodologies
Solid knowledge of ASIC verification methodology
Experience writing micro-architecture spec
Experience converting micro-architecture spec to RTL design
Solid knowledge of RTL coding for synthesis using Verilog
Solid knowledge of RTL coding for DFX
Experience with Synopsys Design Compiler
Experience with Timing analysis and timing closure
Experience with gate level simulations and debug
Excellent written and verbal communication skills
Required Tool knowledge:
VCS, Design Compiler (synthesis)
Verilog/System Verilog, Unix C-shell, Source Code Management
Nice to Have:
Architecture: IA, ARM, embedded controllers
Protocols : DDR, PCIE, AMBA
Tools: Lint, FPV, Perl, Tcl
Desired Max Hourly Rate: Open at Market Rate
Solid knowledge of ASIC design flows and methodologies
Solid knowledge of ASIC verification methodology
Experience writing micro-architecture spec
Experience converting micro-architecture spec to RTL design
Solid knowledge of RTL coding for synthesis using Verilog
Solid knowledge of RTL coding for DFX
Experience with Synopsys Design Compiler
Experience with Timing analysis and timing closure
Experience with gate level simulations and debug
Excellent written and verbal communication skills
Required Tool knowledge:
VCS, Design Compiler (synthesis)
Verilog/System Verilog, Unix C-shell, Source Code Management
Nice to Have:
Architecture: IA, ARM, embedded controllers
Protocols : DDR, PCIE, AMBA
Tools: Lint, FPV, Perl, Tcl
Desired Max Hourly Rate: Open at Market Rate
Consulting | Staffing | Outsourcing