Position: DESIGN VERIFICATION ENGINEER
Location: AUSTIN, TX
Duration: 6-18 months
USC or GCs are encouraged to apply
Job Description:
Jr resources needed
Clients’ group is responsible for creating
several cluster test benches for advanced Ethernet controllers that combine
networking, storage, and high performance computing functionality at 10/40Gb
speeds. These test benches are implemented using the Specman `e' language with
UVM. As part of the pre-silicon Architectural Validation (AV) team you'll help
develop test plans from architecture and design specifications, design test
benches, write tests, gather and analyze coverage results, plug coverage holes,
and debug problems in the design and AV environment. Knowledge of the following
is a plus: Ethernet, TCP/IP, any protocols running on top of TCP, digital logic
simulation, OVM/UVM/VMM, System Verilog, Specman, C++.
Skill Type Skill Level Primary Skill
Verification Basic Yes
Verilog Basic No
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