Design Engineer
Location: Santa Clara, CA
Duration: 7-18 months
USC or GCs are encouraged to apply
RTL coding to implement chipset functionality per Cspec, HAS, MAS. Work closely with pre-si validation tea m to debug failing tests; work closely with Physical Design team to resolve timing closure issues. Document functionality, usage models as required to support stakeholders.
Required skills:
Solid knowledge of ASIC design flows and methodologies
Solid knowledge of ASIC verification methodology
Experience writing micro-architecture spec
Experience converting micro-architecture spec to RTL design
Solid knowledge of RTL coding for synthesis using Verilog
Solid knowledge of RTL coding for DFX
Experience with Synopsys Design Compiler
Experience with Timing analysis and timing closure
Experience with gate level simulations and debug
Excellent written and verbal communication skills
Required Tool knowledge:
VCS, Design Compiler (synthesis)
Verilog/System Verilog, Unix C-shell, Source Code Management
Additional Skills Desired (Nice to Have):
Architecture: IA, ARM, embedded controllers
Protocols : DDR, PCIE, AMBA
Tools: Lint, FPV, Perl, Tcl
Consulting | Staffing | Outsourcing