Position: Design
engineer
Location: Santa Clara
ca
Duration: 6-18 months
USC or GCs
are highly encouraged to apply
Job Description:
10 + years experience required
1.Expertise in RTL: Verilog, VHDL
2.Test environments and methodologies: System Verilog, Specman
3.Experience in debugging and resolving issues across the design flow. Will require knowledge of unix, scripts, debugging tools, waveforms viewers and common design methods.
4.Expertise in revision control tools
5.Good communication skills: interaction with large design team is needed
1.Knowledge of GIT
2.Expertise in display processing
1.Expertise in RTL: Verilog, VHDL
2.Test environments and methodologies: System Verilog, Specman
3.Experience in debugging and resolving issues across the design flow. Will require knowledge of unix, scripts, debugging tools, waveforms viewers and common design methods.
4.Expertise in revision control tools
5.Good communication skills: interaction with large design team is needed
1.Knowledge of GIT
2.Expertise in display processing