VALIDATION
ENGINEER
Location: Santa Clara
CA
Duration: 5-18 MONTHS
USC or GCs
are encouraged to apply
Job Description:
Creating verification environment for the FPGA
simulation. Reuse of IP level tests. Validation and debugging.
Validation using system Verilog/OVM. Creation and reuse of the verification components. Debugging of the design failures. Usage of Simulation tools like VCS.
FPGA knowledge PCie and MIPI protocol
Validation using system Verilog/OVM. Creation and reuse of the verification components. Debugging of the design failures. Usage of Simulation tools like VCS.
FPGA knowledge PCie and MIPI protocol
10 years in Semiconductor industry with 5 years of
verification of digital design. Proficient in System verilog, OVM PCIe protocol
knowledge MIPI protocol knowledge is preferable Shell/C script knowledge FPGA
simulation is preferable.
C; Debug; FPGA; Scripting; Simulation; TESTING; Verilog
C; Debug; FPGA; Scripting; Simulation; TESTING; Verilog